Nvidia Is Financing Billions in Chip Packaging Capacity at ASE's SPIL, Executive Says

The executive said the money would pay for new factory space and equipment for chip-on-wafer-on-substrate (CoWoS) packaging. In this process, AI processors and high-bandwidth memory are joined into a single package so they can work together at high speed. Nvidia did not respond to a request for comment, and ASE said it does not comment on market rumours involving its customers.

If confirmed, the deal would mean the world's most valuable chip designer is paying directly for a supplier's capacity. Packaging, once a low-profile final step in chipmaking, now limits how many top-end AI accelerators can be shipped. TSMC leads the most advanced packaging methods, including CoWoS, which is used by Nvidia, AMD, Broadcom and cloud companies that design their own AI chips. TSMC's limited capacity has pushed those customers to look for other suppliers.

"Everyone is looking for a solution outside TSMC," D.K. Tsai, chairman of Taiwanese packaging company Powertech Technology, said in August.

The market is growing fast. Research firm Yole Group forecasts that revenue from advanced packaging will exceed revenue from traditional packaging for the first time this year, and that capital spending on the technology will approach $28 billion.

Pat Gelsinger, the former Intel chief executive who is now a partner at venture firm Playground Global, said the industry used to treat the step as an afterthought. "Packaging was always that thing that you just did not worry about," he said. He estimated that advanced packaging could eventually account for as much as half of a chip product's value, since some processors now combine 10 or more chips, and sometimes as many as 20.

SPIL was already expanding before the reported Nvidia financing. In August it began building a plant in Douliu, in Yunlin county, that will offer CoWoS packaging. The first phase is due to start operating in 2028, at a cost of about NT$100 billion.

Nvidia's rivals are spending too. AMD has announced more than $10 billion of investments across Taiwan's semiconductor industry, including packaging partnerships with ASE, SPIL and Powertech. "I think CoWoS and advanced packaging are super important for our high-performance computing going forward," AMD chief executive Lisa Su said, adding that the company needs more capacity overall.

Powertech is backing panel-level packaging, which uses large rectangular panels instead of round silicon wafers. It is working with AMD and Broadcom on the technology and plans to invest $400 million in a joint venture with Broadcom in Singapore, where production could begin in 2028. "The most important thing right now is capacity," said Jim Lin, a senior vice president at Powertech. TSMC built a pilot line in April for its own panel-based method, chip-on-panel-on-substrate, and expects production within a couple of years, though CoWoS remains its main AI packaging technology.

Microsoft's Azure hardware chief, Rani Borkar, said panel-level packaging would reduce material waste when packaging larger AI chips, but Microsoft has not decided whether or when to use it.

Equipment makers that have focused on earlier stages of chipmaking are moving into the field. Seiji Nakama, president of Tokyo Electron Taiwan, said advanced packaging is growing much faster than the chipmaking equipment market, although it is still smaller. Sree Kesapragada, a vice president at Applied Materials, said the packaging market, including panel-level technology, could grow significantly within three to five years. "It is near-term. It is not like, 10 years, 15 years off," he said.